Processing of silicon wafers is commonplace in the manufacture of modern microelectronics devices. Such processing, including plasma processing and ion implantation may be performed at low pressures, wherein RF or microwave plasmas, or high-power particle beams are delivered to the wafer, therein producing high temperatures at the wafer during processing. Such high temperatures (e.g., temperatures exceeding 100 C for conventional implants, and up to 400 C for other processes), however, can have deleterious effects on the wafer.
For many processes, precise temperature control is not required, as long as the wafer temperature remains at less than a predetermined limit, such as below 100 C in ion implantation or less than 400 C in general. Current trends in ion implantation, however, are tending toward high power serial implanters which generally require cooling with heat transfer coefficients HTC>200 mW/cm2C and temperature control within ±5%. In advanced implant and wafer processing operations, a precise temperature control is typically required, wherein HTC uniformity across a 300 mm wafer, for example, needs to be maintained within 1%. Such processes can have an HTC value, for example, as high as 500 mW/cm2C.
Wafer temperature control and the issues related in semiconductor processing has utilized electrostatic chucks (ESCs) for some time. A typical single-polar ESC is illustrated in FIG. 1, wherein the ESC 10 holds the wafer 20 in place by electrostatic force. The wafer 20 is separated from an electrode 30 by an insulating layer 40. A voltage (e.g., illustrated as a +) is applied to the electrode 30 by a voltage source 50. The voltage applied to the electrode produces an electrostatic field (e.g., illustrated as a “−”) at the wafer 20 which induces an equal and opposite charge (e.g., illustrated as a +) on the wafer 20. The electrostatic field on the wafer 20 produces an electrostatic force between the wafer and the ESC 10. Consequently, the electrostatic force holds the wafer 20 against the insulating layer 40.
Cooling of the wafer 20 when utilizing ESCs can be provided by contact conductivity between the wafer and the contact surface 60 of the insulating layer 40, wherein the insulating layer may be cooled by cooling water or a cooling medium. Conventionally, the cooling of the wafer 20 generally increases with the voltage applied to the ESC. Significantly high voltages, however, can have deleterious effects on the wafer (e.g., a cause of particle generation), and may further have costly power supply and consumption considerations, along with increased failure rates. Additionally, the temperature differential created between the warm environment of a processing chamber where the ESC may be located and the internal cooling of the ESC can generate condensation, along with component failure.
In vacuum environments, conventional ESCs utilize a cooling gas between the wafer 20 and the insulating layer 40, wherein a contact surface 60 of the insulating layer 40 comprises a plurality of protuberances (not shown) machined into the insulating layer, therein providing a region for the cooling gas to reside. Typically, a ceramic layer is conventionally machined to form protuberances therein, wherein the protuberances can be formed by bead blasting.
Although low-temperature ion implantation has been attempted, existing approaches suffer from a number of deficiencies. For example, exposure of the vacuum chamber to the low-temperature wafers and/or cooled chucks may result in residual moisture or condensable material (e.g., water) on the outside of the chuck surface while operating at low temperatures, which may cause icing.
In view of the foregoing, it would be desirable to provide a solution for low-temperature ion implantation for use in high-throughput ion implanters which overcomes the above-described inadequacies and shortcomings.